VLSI Architecture for SISO Equalizer

Description

‘Intersymbol interference (ISI)’ is the main factor that affects the performance of digital as well as wireless communication. Linear turbo equalization is a form of joint equalization and decoding in which soft information is iteratively exchanged between the SISO (Soft Input Soft output) equalizer and SISO decoder. Decision feedback equalizers are used in wireless and mobile communications to reduce the intersymbol interference that is caused by the time dispersive channel. SISO equalization is a recently developed technique for combating ISI with a higher degree of computational efficiency even in the presence of high spectral efficiency modulation schemes. An adaptive decision feedback equalizer used for SISO equalizer is presented with a new adaptive algorithm. The algorithm uses sign normalized block-based modified least mean square algorithm and achieves a significant reduction of computational complexity. The proposed algorithm exhibit dramatic bit error rate improvement over a reasonable signal to noise ratio also, it separate reckons of error-computation block and weight-update block for Proakis channels. Comparative analyses of various Adaptive equalizer algorithms for two different frequency scenario are also contemplated. The frequency-domain representation facilitates us to choose step size in an easier way so that the proposed algorithm can converge in mean square perception. Simulation studies show that the proposed realization gives better performance compared to existing conventional analysis methods in terms of bit error rate (BER) and convergence rate.

About The Author

Mr. Samir Mishra, currently serving as Assistant Director | Research & Development (R&D) at Rama University, Kanpur, UP. He has received B. Tech, M.Tech degree in Electronics & Communication Engineering (in VLSI & Microelectronics) from the Indian Institute of Technology, Kharagpur in 2012. Since then he has contributed significantly in the field of academia and research. He has experience in Indian Space Research Organization (ISRO) on MEMS and has received National Merit Scholar Award by MHRD Scholarship by Government of India. He has been nominated for an Outstanding Research Award for his contributions to the field of engineering & research. Currently, he has been associated with Rama University and holds significant positions and responsibilities. He has served as Head of Departments for the Department of Electronics & Communication and has also worked as a Dean (Student Welfare) for Rama University and is currently serving as an Assistant Director- Research & Development. He has successfully organized more than 8 international conferences and is a member of the Editorial Board for the International Journal. He is also an active member of the IQAC/IPR committee and has filed for numerous patents, copyright & research paper (IEEE Transactions) mostly in Electronics to serve the nation in the field of research. He is also an IEEE-Reviewer and part of the technical committee of ICACCI as a reviewer.